1. Field of the Invention
The present invention relates to a magnetic memory device, and more particularly, to a magnetic memory device having write word lines, which indicate word lines to be used during a write operation, and read word lines, which indicate word lines to be used during a read operation.
2. Description of the Related Art
As a magnetic memory device, a magnetic random access memory (MRAM) is known. In a memory cell of an MRAM, a device having a magnetic tunnel junction (MTJ) is used. An MTJ device is formed of two ferromagnetic films (one serving as a pinned layer (fixed layer); the other as a recording layer (free layer)) and a single dielectric film (serving as a tunnel barrier layer) sandwiched between the two ferromagnetic films.
FIG. 21 is a cross sectional view of a typical memory cell (MC) of an MRAM. To write data, current is passed through a write word line (Write Word Line) WW and crossing a bit line B at right angles, thereby producing a magnetic field at the intersection between the bit line B and the write word line WW. This magnetic field reverses the direction of magnetization of the recording layer of the MTJ device MTJ. Depending on the relative orientation (either parallel or nonparallel) of the magnetization of the recording layer with respect to the pinned layer, binary 0 or binary 1 is written.
The data is read by using the tunneling magnetoresistive (TMR) effect, a phenomenon in which the electric resistance of the MTJ device MTJ changes with the relative angle between the direction of magnetization of the ferromagnetic film forming the MTJ device MTJ and the current direction. Specifically, first the read word line (Read-Word-Line) RW is driven to turn on a memory cell transistor TR, so that current flows from the bit line B to a ground GND via the MTJ device MTJ, and then the signal current is detected by a sense amplifier (not shown) connected to the bit line B, the resistance mentioned above can be detected.
FIG. 22 is a circuit diagram of the memory cell shown in FIG. 21. FIG. 23 is a conventional circuit diagram showing a memory cell array including memory cells of the type shown in FIG. 22 and the peripheral portion. As shown in FIG. 23, memory cells MC[0,0] to MC[m, n] are arranged at the intersections of a set of write word lines WW[0] to WW[m] and read word lines RW[0] to RW[m], and bit lines B[0] to [n]. Bit line drivers BDU[0] to BDU[n], which are positioned above the memory cell array MCA, and bit line drivers BDL[0] to BDL[n], which are positioned below the memory cell array MCA, drive bit lines B[0] to B[n], respectively. The two ends of each of corresponding write word lines WW[0] to WW[n] are connected to the corresponding write word line drivers WWD[0] to WWD[n] and current sinkers WS[0] to WS[n], respectively. During a write operation, a write current flows by activating one of the pairs of the write word line driver WWD[i] and the current sing circuit WS[i], where i=0, 1, . . . , n.
A large current is supplied to the write word lines WW (WW[0] to [m]) to generate magnetic fields in the memory cells MC (MC[0,0] to MC[m, n]). Therefore, the write word lines are generally formed of a low-resistance metal. On the other hand, it is not necessary to supply such a large current to the read word lines RW (RW[0] to RW[m]). For this reason, the read word lines RW are formed of a relatively high-resistance material (e.g., polysilicon), which is usually used in the gate electrode of a memory cell transistor TR.
As described above, a read word line RW has a resistance about 10 to 100 times larger than that of a write word line WW. In addition, since the read word line RW is the gate electrode of a memory cell transistor TR, it has a large capacitance. As a result, the product of resistance and capacitance (RC) of the read word line RW becomes large, which degrades an operation speed. The problem of read-speed reduction becomes severe in a large-scale memory cell array (MCA). To avoid this problem, the memory cell array MCA must be limited in size.
To overcome the above problems, a second conventional circuit design is proposed in FIG. 24 in which a single read word line RW and a single write word line WW are shown. As shown in FIG. 24, a word line control circuit WCTR is connected to both ends of the write word line WW. The write word line WW and the read word line RW are connected by a shunt ST. One end of a memory cell transistor TR is connected to the common node CN, which is grounded via a connection transistor S. Since the read word line RW is connected to the write word line WW, the effective resistance value of the read word line RW becomes lower than that in the first conventional circuit. To prevent the transistor TR from being turned on by the current flowing through the read word line RW during the write operation, the common node CN is isolated from the ground by the connection transistor S.
However, in the second conventional circuit design, since the read word line RW and the write word line WW are connected via the shunt ST, the following problems may occur. First, since the shunt ST takes up space, the area occupied by the memory cell array MCA increases. Second, the periodical layout pattern of the memory cell array MCA breaks by the presence of the shunt ST. This collapse of the periodicity makes submicron lithography more difficult.